The present invention relates to a gradation corrector used in correcting the gradation of a video signal in a television receiver, a video tape recorder, a video camera, a video disk or the like.
In recent years, great importance has been attached to a gradation corrector in order to provide a more clear image which is required with the increase in size of a color television receiver and the improvement in image quality thereof, and more especially, in order to expand the dynamic range of an image on a CRT by passing a video signal through a non-linear amplifier to correct the gradation of the video signal.
FIG. 4 shows a block diagram of a gradation corrector proposed precedently to the present application. In FIG. 4, reference numeral 1 designates an A/D converter for converting an input luminance signal into a digital value. Numeral 2 designates a histogram memory for obtaining a luminance distribution of the input luminance signal. In general, the luminance level enters an address of the memory 2 and the frequency enters as data thereof. Numeral 3 designates a histogram operating circuit for computing histogram features such as mean value, mode value, minimum value, maximum value, deviation coefficient, white area, black area, etc. of the input luminance signal from the data of the histogram memory 2 and computing control values inclusive of a limiter level, the value of addition, an accumulation start luminance level, an accumulation stop luminance level, the maximum luminance level and so on from the determined values to output the control values to a limiter/adder circuit 5, an accumulation control register circuit 6 and a normalization control register circuit 7. The limiter/adder circuit 5 is provided for processing the data of the histogram. Namely, on the basis of data transferred from the histogram operating circuit 3, the limiter/adder circuit 5 imposes a limitation on the data of the histogram so that it does not exceed a certain level and performs the operation of addition. In general, the data processing performed by the limiter/adder circuit 5 is completed during a time when the address is accessed once. The accumulation start and stop luminance levels, at which the accumulation is to be started and stopped in determining a cumulative histogram, are supplied from the histogram operating circuit 3 to the accumulation control register circuit 6 which in turn controls a histogram accumulation circuit 8.
The histogram accumulation circuit 8 makes the accumulation of processed data from the histogram memory 2 on the basis of a control signal from the accumulation control register circuit 6. Numeral 9 designates a cumulative histogram memory for storing therein the result of accumulation by the histogram accumulation circuit 8. In general, the luminance level enters an address of the memory 9 and the frequency enters as data thereof. In normalizing data of the cumulative histogram to produce a look-up table, the maximum luminance level for an output luminance signal after normalization is supplied from the histogram operating circuit 3 to the normalization control register circuit 7 and the normalization control register circuit 7 controls a normalization coefficient in accordance with the value of the maximum luminance level. Numeral 10 designates a look-up table operating circuit which normalizes the data of the cumulative histogram memory 9 in accordance with an output of the normalization control register circuit 7. Numeral 11 designates a look-up table memory for storing therein the data normalized by the look-up table operating circuit 10. In general, the luminance level of the input signal enters an address of the memory 11 and the normalized data enters an data thereof. Numeral 12 designates a timing control circuit which makes the sequencing of various operations and the control for the memories. Numeral 13 designates a D/A converter by which output data corrected by use of the look-up table is converted into an analog value.
Next, explanation will be made of the operation of the gradation corrector having the above construction. FIGS. 5A to 5F show operating waveforms of various parts.
First, an input luminance signal a is inputted to the A/D converter 1 and is converted thereby into a digital value which is in turn outputted as a converted input luminance signal b. The converted input luminance signal b is taken as a memory address of the histogram memory 2 and data at that address is processed by the limiter/adder circuit 5. By performing this operation during one vertical scanning interval, it is possible to obtain a histogram distribution of the input luminance signal a. The histogram distribution is shown in FIG. 5A.
Next, data of the histogram memory 2 including the histogram distribution is read by the histogram operating circuit 3 which in turn calculates the mean value, the mode value, the minimum value, the maximum value, the deviation coefficient, the white area, the black area, etc. of the input luminance signal. The histogram operating circuit 3 further determines control values inclusive of a limiter level, the value of addition, an accumulation calculation start luminance level, an accumulation calculation stop luminance level, the maximum luminance level after normalization and so on from the result of the above calculation and transfers the determined data to the limiter/adder circuit 5, the accumulation control register circuit 6 and the normalization control register circuit 7.
Thereafter, the limiter/adder circuit 5 reads data from the histogram memory 2 to make a limiter (see FIG. 5B) and the operation of addition or the like for each read data on the basis of each data transferred from the histogram operating circuit 3 and outputs the result (or corrected histogram data c) to the histogram accumulation circuit 8 (see FIG. 5C). In the case where the value of addition is fixed, a curve obtained by the cumulative addition becomes nearer to a linear profile as the value of addition is larger and approaches to a histogram flatting process as the value of addition is smaller (see FIGS. 5C and 5D).
On the basis of the accumulation start luminance level and the accumulation stop luminance level supplied from the accumulation control register circuit 6, the histogram accumulation circuit 8 calculates cumulative histogram data f from the corrected histogram data c in a range between the accumulation start and stop luminance levels and causes the cumulative histogram memory 9 to store the result of calculation.
Next, the look-up table operating circuit 10 reads the cumulative histogram data from the cumulative histogram memory 9 to determine a normalization coefficient so that the maximum value of the cumulative histogram data becomes the maximum output luminance level h supplied from the normalization control register circuit 7. The look-up table operating circuit 10 performs an operation on all the cumulative histogram data g by use of the determined normalization coefficient and causes the look-up table memory 11 to store the result i. If the maximum output luminance level is controlled, an operation such as an automatic contrast control (ACL) or an automatic brightness control (ABL) is possible. Such an operation is shown in FIG. 5E.
Thereafter, data in the look-up table memory 11 is read with the converted input luminance signal b being used as an address and the read data is outputted as a corrected output luminance signal j. FIG. 5F shows a histogram of the corrected output luminance signal j. The D/A converter 13 outputs the corrected output luminance signal j after conversion thereof into an analog signal k.
The timing control circuit 12 controls the operations of various circuits so that the operations of respective parts are performed at such timings as mentioned above. [For example, refer to Japanese Patent Application No. (Hei)1-265393 (JP-A-3-126,377), entitled "Gradation Corrector", filed by the applicant of the present application.] The gradation corrector proposed in the preceding application JP-A-3-126,377 is of a same type as the above corrector shown in FIG. 4 and adapted to be capable of sufficiently effecting gradation correction on signals of bright levels and intermediate luminance levels as well as on those of black side, and yet capable of effecting gradation correction of higher fidelity and higher contrast, while capable of preventing over-extension of dynamic range. These gradation corrections are effected, as above noted, by adding or subtracting preselected values to or from the data of histogram, substituting preselected values for that of higher or lower than a certain value, thereby optimizing effects of histogram flatting processing, and by controlling range of histogram data to be accumulated or controlling the maximum of the normalized data. In an embodiment of the preceding application, the histogram operating circuit comprises an average luminance level computing circuit for computing from data of the histogram memory an average value of input luminance signal, a mode luminance level detection circuit for detecting a mode value, maximum and minimum detection circuits, a circuit for computing a deviation (dispersion) coefficient from data of the histogram memory, and a computing circuit for computing white and black areas. With these circuits the histogram operating circuit is adapted to further compute the control values such as limiter level, accumulation start/stop luminance level, etc. The average value of input luminance signal is computed from the histogram memory data and along the following equation (). ##EQU1## The mode value designates an input luminance signal level causing a maximum of histogram data. The maximum value detected by the detection circuit designates an input luminance level corresponding to an upper limit of the histogram distribution, and the detected minimum value designates an input luminance level corresponding to a lower limit of the histogram distribution. The black area designates picture elements of input signal luminance levels, for example, in a luminance range of 0 to 40% of the histogram distribution while the white area designates picture element of input signal luminance levels, for example, in a luminance range of more than 60% of the histogram distribution. The deviation coefficient may be calculated as a standard deviation or alternatively may be calculated simply along the following equation (2). ##EQU2## The histogram operating circuit 3 of the gradation corrector shown in present FIG. 4 is substantially the same constitution and function as the preceding circuit just mentioned.
In the above type gradation correctors, however, since the minimum value of the histogram to be detected is an instantaneous value detected from the histogram in one vertical scanning interval, there is a problem that if many noises are included in a video signal, the minimum value detected has a great variation with the result that the corrected output luminance signal oscillates, which value may affect to such corrected output luminance signal more significantly than other histogram features.